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[VHDL-FPGA-Verilog] FIFO_Buffer

Description: Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
Platform: | Size: 1024 | Author: david | Hits:

[Program doc] 68013_SlaveFIFO

Description: cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
Platform: | Size: 2151424 | Author: 杨瑞 | Hits:

[VHDL-FPGA-Verilog] fifo_test

Description: FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
Platform: | Size: 2048 | Author: saul | Hits:

[VHDL-FPGA-Verilog] parallel-fifo

Description: 利用Verilog语言编写的并行数据传输程序，在编译环境中编译通过。- the model of parallel data transmit which is written of verilog.
Platform: | Size: 5120 | Author: saul | Hits:

[OS Develop] fifo

Description: 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
Platform: | Size: 5120 | Author: 颜良飞 | Hits:

[VHDL-FPGA-Verilog] asymmetric_fifo

Description: 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
Platform: | Size: 11264 | Author: claud | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 简易环形FIFO的设计、简单异步串行通信接口设计等-verilog
Platform: | Size: 619520 | Author: 柳澈 | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
Platform: | Size: 62464 | Author: 张晗 | Hits:

[Other] fifo

Description: fifo 即实现数据的先进先出，是用verilog编写的 就撒开了几分-fifo hjahfjhsjeikkdnakfnakjfakjkf
Platform: | Size: 1024 | Author: leo | Hits:

[USB develop] asfifodesign

Description: 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
Platform: | Size: 545792 | Author: 何正文 | Hits:

[Other] fifo

Description: FIFO verilog controller, asyn. circuit
Platform: | Size: 2048 | Author: lai | Hits:

[VHDL-FPGA-Verilog] pgm

Description: uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
Platform: | Size: 205824 | Author: libin | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 速度高达130MHz 可实现高速数据采集 程序源码为Verilog-Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
Platform: | Size: 116736 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] TERASIC_AUDIO

Description: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Platform: | Size: 125952 | Author: changjiang | Hits:

[Other] fifo

Description: 使用verilog语言编写的fifo程序。-Use the fifo verilog language program.
Platform: | Size: 3072 | Author: 小刘 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] sfifo

Description: verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] Decoy

Description: 外部 FIFO 的控制 verilog语言-verilog FIFo
Platform: | Size: 1024 | Author: xuxf | Hits:

[VHDL-FPGA-Verilog] fifolifo

Description: fifo filo verilog 程序！先入先出数据存储器的程序和先入后出程序！-fifo filo verilog program! First in first out data memory of the program!
Platform: | Size: 1024 | Author: qixia | Hits:
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